WORLDTECHNVIDIA lowers HBM4 pin speed and NVL72 memory bandwidth for Vera Rubin
NVIDIA has revised target specifications for its Vera Rubin product line, cutting the per-pin speed of its HBM4 memory and the total memory bandwidth of the Vera Rubin NVL72 rack-scale system, according to a report by TechPowerUp.
Lower memory and bandwidth targets
According to an updated product specification sheet cited by TechPowerUp, NVIDIA has officially implemented changes across the Vera Rubin line that reduce target figures for memory and interconnect fabric. For the Vera Rubin NVL72 rack-scale solution, the advertised total memory bandwidth now stands at 1,400 TB/s, down from the previously advertised 1,580 TB/s.
The first change concerns HBM4. Where NVIDIA had previously specified HBM4 at 11.7 Gbps per pin, the updated sheet lists 9.6 Gbps per pin.
Signalling design cited as the limiting factor
The report indicates that the issue does not originate with NVIDIA's suppliers. Instead, it suggests that the company's implementation of memory bus width and overall electrical signalling is not sufficient to support the higher speeds originally targeted.
The changes are not confined to memory. The report notes that further adjustments also apply elsewhere in the product line, though the facts available do not detail them.
Open questions
- Which interconnect specifications beyond memory have been changed?
- Will NVIDIA publicly explain the reasons for the revised targets?