Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations

What happened

Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations, according to Semiconductor Engineering. Part 2: Towards scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability. Key takeaways: From the A7 logic technology node onwards, industry may likely transition to CFET-based transistor architectures which enable 4.5-track (4.5T) and below standard cells.

Progress in CFET enablement is backed by two complementary R&D tracks, with imec pioneering many of the underlying innovations: the development of CFET-specific process modules, and a design-technology co-optimization (DTCO) exploration of scalable standard cell configurations. Part 1 of this two-part article presents two optimized CFET-specific modules: (1) a backside contact module; and (2) a gate-stack integration module that enables multiple threshold voltages in nanosheet and CFET devices. Part 2 covers imec’s latest CFET DTCO studies.